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ACPM-5007 lte band7 (2500-2570 mhz) 3 x 3 mm power amplifi er module data sheet features ? thin package (0.9 mm typ) ? excellent linearity ? 3-mode power control with vbp and vmode bypass/mid power mode/high power mode ? high effi ciency at max output power ? 10-pin surface mounting package ? internal 50 ohm matching networks for both rf input and output ? integrated coupler coupler and isolation ports for daisy chain ? green C lead-free and rohs complian applications ? umts & lte band7 handset, data card ordering information part number number of devices container ACPM-5007-tr1 1000 178 mm (7) tape/reel ACPM-5007-blk 100 bulk description the ACPM-5007 is a fully matched 10-pin surface mount module developed for lte band7. this power amplifi er module operates in the 2500-2570 mhz bandwidth. the ACPM-5007 meets stringent umts (rel 99) linearity re- quirements up to 28.5 dbm output power and the lte (mpr = 0 db) to 27.5 dbm. the 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks. the ACPM-5007 features 5 th generation of coolpam circuit technology which supports 3 power modes C bypass, mid and high power modes. the coolpam is stage bypass technology enhancing pae (power added effi ciency) at low and medium power range. active bypass feature is added to 5 th generation to enhance pae further at low output range. this helps to extend talk time. a directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain. a directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain . the integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. the coupler directivity, or the output power variation into the mismatched load, is critical to the trp and sar per- formance of the mobile phones in real fi eld operations as well as compliance tests for the system specifi cations. the ACPM-5007 has integrated on-chip vref and on-module bias switch as the one of the key features of the coolpam-5, so an external constant voltage source is not required, eliminating the external ldo regulators and switches from circuit boards of mobile devices. it also makes the pa fully digital-controllable by the ven pin that simply turns the pa on and off from the digital control logic input from baseband chipsets. all of the digital description (cont.) control input pins such as the ven, vmode and vbp are fully cmos compatible and can operate down to the 1.35 v logic. the current consumption by digital control pins is negligible. the power amplifi er is manufactured on an advanced ingap hbt (hetero-junction bipolar transistor) mmic (microwave monolithic integrated circuit) technology off ering state-of-the-art reliability, temperature stability and ruggedness.
2 absolute maximum ratings no damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. description min. typ. max. unit rf input power (pin) 0 10.0 dbm dc supply voltage (vcc1, vcc2) 0 3.4 5.0 v enable voltage (ven) 0 2.6 3.3 v mode control voltage (vmode) 0 2.6 3.3 v bypass control (vbp) 0 2.6 3.3 v storage temperature (tstg) -55 25 +125 c recommended operating condition description min. typ. max. unit dc supply voltage (vcc1, vcc2) 3.2 3.4 4.2 v enable voltage (ven) low high 0 1.35 0 2.6 0.5 3.1 v v mode control voltage (vmode) low high 0 1.35 0 2.6 0.5 3.1 v v bypass control voltage (vbp) low high 0 1.35 0 2.6 0.5 3.1 v v operating frequency (fo) 2500 2570 mhz ambient temperature (ta) -20 25 90 c operating logic table power mode ven vmode vbp pout (rel99) pout (lte mpr = 0 db) high power mode high low low ~ 28.5 dbm ~ 27.5 dbm mid power mode high high low ~ 17 dbm ~ 16 dbm bypass mode high high high ~ 7 dbm ~ 6 dbm shut down mode low low low C C
3 electrical characteristics C conditions: vcc = 3.4 v, ven = 2.6 v, ta = 25 c, zin/zout = 50 ohm characteristics condition min. typ. max. unit operating frequency range ? 2500 C 2570 mhz maximum output power (high power mode) wcdma rel99 28.5 dbm lte mpr = 0 db 27.5 dbm gain (lte mpr = 0 db) high power mode, pout = 27.5 dbm 25 28 db mid power mode, pout = 16 dbm 17 21 db bypass mode, pout = 6 dbm 8 10.5 db power added effi ciency high power mode, pout = 28.5 dbm, rel99 C 41.6 % high power mode, pout = 27.5 dbm, lte mpr = 0 db 33.0 36.7 mid power mode, pout = 16 dbm, lte mpr = 0 db 14.5 19.4 % bypass mode, pout = 6 dbm, lte mpr = 0 db 5.9 8.2 % total supply current high power mode, pout = 28.5 dbm, rel99 500 Cma high power mode, pout = 27.5 dbm, lte mpr = 0 db 450 500 mid power mode, pout = 16 dbm, lte mpr = 0 db 60 80 ma bypass mode, pout = 6 dbm, lte mpr = 0 db 13 20 ma quiescent current high power mode 105 150 ma mid power mode 18 30 ma bypass mode 4 6ma enable current high power mode 3.7 100 ? a mid power mode 3.8 100 ? a bypass mode 3.8 100 ? a mode control current mid power mode 3.7 100 ? a bypass mode 3.9 100 ? a bypass control current bypass 3.8 100 ? a total current in power-down mode ven = 0 v, vmode = 0 v, vbp = 0 v 3.5 10 ? a lte adjacent channel leakage ratio e-utra aclr pout < (maximum power Cmpr) -37 -33 dbc utra aclr1 pout < (maximum power Cmpr) -39 -36 dbc utra aclr2 pout < (maximum power Cmpr) -60 -39 dbc harmonics 2 fo 3 fo and higher high power mode, pout = 28.5 dbm -35 -42 dbc dbc harmonic gain 2 fo 3 fo and higher where g is gain in tx band g-40 db db input vswr ? 2:1 stability (spurious output) vswr 5:1, all phase -70 dbc rx band noise power high power mode, pout = 28.5 dbm -136 dbm/hz rx band gain where g is gain in tx band g-2 db gps band noise power (1574-1577 mhz, vcc = 4.2 v) high power mode, pout = 28.5 dbm -140 dbm/hz gps band gain where g is gain in tx band g-11 db ism band noise power 2400 ~ 2420 mhz -115 dbm/hz 2420 ~ 2440 mhz -106 dbm/hz 2440 ~ 2460 mhz -98 dbm/hz 2460 ~ 2480 mhz -85 dbm/hz ism band gain where g is gain in tx band g-0.25 db media band gain (716-728 mhz) where g is gain in tx band g-25 db phase discontinuity low power mode ? mid power mode, at pout = 7 dbm mid power mode ? high power mode, at pout = 17 dbm 12 10 deg deg ruggedness pout < 28.5 dbm, pin < 10 dbm, all phase high power mode 10:1 vswr coupling factor rf out to cpl port 20 db daisy chain insertion loss iso port to cpl port, 698 ~ 2620 mhz, ven = low 0.25 db
4 footprint and pin description x-ray top view all dimensions are in millimeter 0.125 0.10 0.35 0.35 0.60 0.10 1.50 0.25 0.3 pin 1 vcc1 rfin vpp vmode ven vcc2 rfout iso gnd cpl 1 2 3 4 5 10 9 8 7 6 pin # name description pin # name description 1 vcc1 dc supply voltage 6 cpl coupling port of coupler 2rfin rf input 7 gnd ground 3vbp bypass control 8 iso isolation port of coupler 4 vmode mode control 9 rfout rf out 5 ven pa enable 10 vcc2 dc supply voltage
5 package dimensions marking specifi cation pin 1 mark manufacturing part number lot number p manufacturing info yy manufacturing year ww work week aaaaa assemby lot number a5007 pyyww aaaaa all dimensions are in millimeter note: prior to production release, the marking will be e5007. after the completion of avago qualifi cation testing and production release, the marking will revert to a5007. 2 3 4 pi n 1 mar k 1 5 9 8 7 1 0 6 3 0. 1 3 0. 1 0.9 0. 1 0.5
6 metallization solder mask opening solder paste stencil aperture pcb design guidelines the recommended pcb land pattern is shown in fi gures on the left side. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown here. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. con- sidering the fact that solder paste thickness will directly aff ect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm(4 mils) or 0.127 mm(5 mils) thick stainless steel which is capable of producing the required fi ne stencil outline. 0.30 0.60 0.35 0.55 0.45 on 0.5 mm pitch ? 0.3 mm 0.475 connected to a inner layer through a via hole for a better isolation between cpl_in(iso) and rfout 0.65 0.45 0.50 0.60 1.50 1.30 0.525 0.55 0.45 1.10 1.10 0.60 0.35 0.475
7 c1 a5007 pyyww aaaaa c2 c3 c4 c6 c5 c7 evaluation board schematic evaluation board description 1 vcc1 2 rf in 3 vbp 4 vmode 5 ven vcc2 10 rf out 9 gnd 7 cpl 6 ven vmode rf in vcc1 vcc2 isolation c1 100 pf c2 100 pf 2.2 f c6 c7 33 pf c5 2.2 f vbp c3 100 pf iso 8 rf out coupler 50 ohm 1000 pf c4
8 tape and reel information dimension list annote millimeter a0 3.400.10 b0 3.400.10 k0 1.350.10 d0 1.550.05 d1 1.600.10 p0 4.000.10 p1 8.000.10 annote millimeter p2 2.000.05 p10 40.000.20 e 1.750.10 f 5.500.05 w 12.000.30 t 0.300.05 tape and reel format C 3 mm x 3 mm a5007 pyyww aaaaa
9 plastic reel format (all dimensions are in millimeters) reel drawing notes: 1. reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. avago technologies part number c. purchase order number d. date code e. quantity of units 2. a certi?cate of compliance (c of c) shall be issued and accompany each shipment of product. 3. reel must not be made with or contain ozone depleting materials. 4. all dimensions in millimeters (mm) 50 min. 12.4 +2.0 -0.0 18.4 max. 25 min wide (ref) slot for carrier tape insertion for attachment to reel hub (2 places 180 apart) back view front view 178 shading indicates thru slots +0.4 -0.2 21.0 0.8 13.0 0.2 1.5 min.
10 handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environ- ment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the acquired discharge route is through a semiconductor device, de- structive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classifi ed for moisture sensitivity by soaking a known dry package at moisture classifi cation level and floor life msl level floor life (out of bag) at factory ambient = < 30 c/60% rh or as stated 1 unlimited at = < 30 c/85% rh 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 mandatory bake before use. after bake, must be refl owed within the time limit specifi ed on the label note: 1. the msl level is marked on the msl label on each shipping bag. various temperatures and relative humidity, and times. after soak, the components are subjected to three con- secutive simulated refl ows. the out of bag exposure time maximum limits are deter- mined by the classifi cation test describe below which cor- responds to a msl classifi cation level 6 to 1 according to the jedec standard ipc/jedec j-std-020b and j-std-033. ACPM-5007 is msl3. thus, according to the j-std-033 p.11 the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classifi cation refl ow temperature for the ACPM-5007 is targeted at 260 c +0/-5 c. figure and table on next page show typical smt profi le for maximum temperature of 260 +0/-5 c.
11 refl ow profi le recommendations typical smt refl ow profi le for maximum temperature = 260 +0/-5 c profi le feature sn-pb solder pb-free solder average ramp-up rate (t l to t p ) 3 c/sec max 3 c/sec max preheat C temperature min (t smin ) C temperature max (t smax ) C time (min to max) (t s ) 100 c 150 c 60-120 sec 150 c 200 c 60-180 sec t smax to t l C ramp-up rate 3 c/sec max time maintained above: C temperature (t l ) C time (t l ) 183 c 60-150 sec 217 c 60-150 sec peak temperature (t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature (t p ) 10-30 sec 20-40 sec ramp-down rate 6 c/sec max 6 c/sec max time 25 c to peak temperature 6 min max. 8 min max. 25 time temperature t p t l t p t l t 25 c to peak ramp-up t s t smin ramp-down preheat critical zone t l to t p t smax
12 storage condition packages described in this document must be stored in sealed moisture barrier, antistatic bags. shelf life in a sealed moisture barrier bag is 12 months at <40 c and 90% relative humidity (rh) j-std-033 p.7. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours as listed in the j-std-020b p.11 with factory conditions <30 c and 60% rh. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfi ed. baking must be done if at least one of the con- ditions above have not been satisfi ed. the baking condi- tions are 125 c for 12 hours j-std-033 p.8. caution tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200 c. this method will minimize moisture related component damage. if any component temperature exceeds 200 c, the board must be baked dry per 4-2 prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their fl oor life can be exposed to a maximum body temperature as high as their specifi ed maximum refl ow temperature. removal for failure analysis not following the above requirements may cause moisture/ refl ow damage that could hinder or completely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125 c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125 c. batteries and electrolytic capaci- tors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake temperature from table 4-1 in j-std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc-7711 andipc-7721. derating due to factory environmental conditions factory fl oor life exposures for smd packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. this approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30c/60% rh. a solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diff usion in the component package materials ref. jesd22-a120). recommended equivalent total fl oor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table on next page lists equivalent derated fl oor lives for humidities ranging from 20-90% rh for three tempera- ture, 20 c, 25 c, and 30 c. table on next page is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in cal- culating this table: 1. activation energy for diff usion = 0.35ev (smallest known value). 2. for 60% rh, use diff usivity = 0.121exp (-0.35ev/kt) mm 2 /s (this used smallest known diff usivity @ 30 c). 3. for >60% rh, use diff usivity = 1.320exp (-0.35ev/kt) mm 2 /s (this used largest known diff usivity @ 30 c).
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-2977en - may 23, 2011 recommended equivalent total floor life (days) @ 20 c, 25 c & 30 c, 35 c for ics with novolac, biphenyl and multifunctional epoxies (refl ow at same temperature at which the component was classifi ed) maximum percent relative humidity maximum percent relative humidity package type and body thickness moisture sensitivity level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% body thickness 3.1 mm including pqfps >84 pin, plccs (square) all mqfps or all bgas 1 mm level 2a 94 124 167 231 44 60 78 103 32 41 53 69 26 33 42 57 16 28 36 47 7 10 14 19 5 7 10 13 4 6 8 10 35 c 30 c 25 c 20 c level 3 8 10 13 17 7 9 11 14 6 8 10 13 6 7 9 12 6 7 9 12 4 5 7 10 3 4 6 8 3 4 5 7 35 c 30 c 25 c 20 c level 4 3 5 6 8 3 4 5 7 3 4 5 7 2 4 5 7 2 3 5 7 2 3 4 6 2 3 3 5 1 2 3 4 1 2 3 4 35 c 30 c 25 c 20 c level 5 2 4 5 7 2 3 5 7 2 3 4 6 2 2 4 5 1 2 3 5 1 2 3 4 1 2 2 3 1 1 2 3 1 1 2 3 35 c 30 c 25 c 20 c level 5a 1 2 3 5 1 1 2 4 1 1 2 3 1 1 2 3 1 1 2 3 1 1 2 2 1 1 1 2 1 1 1 2 1 1 1 2 35 c 30 c 25 c 20 c body 2.1 mm thickness <3.1 mm including plccs (rectangular) 18-32 pin soics (wide body) soics 20 pins, pqfps 80 pins level 2a 58 86 148 30 39 51 69 22 28 37 49 3 4 6 8 2 3 4 5 1 2 3 4 35 c 30 c 25 c 20 c level 3 12 19 25 32 9 12 15 19 7 9 12 15 6 8 10 13 5 7 9 12 2 3 5 7 2 2 3 5 1 2 3 4 35 c 30 c 25 c 20 c level 4 5 7 9 11 4 5 7 9 3 4 5 7 3 4 5 6 2 3 4 6 2 3 4 5 1 2 3 4 1 2 2 3 1 1 2 3 35 c 30 c 25 c 20 c level 5 3 4 5 6 2 3 4 5 2 3 3 5 2 2 3 4 2 2 3 4 1 2 3 4 1 1 2 3 1 1 1 3 1 1 1 2 35 c 30 c 25 c 20 c level 5a 1 2 2 3 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 0.5 0.5 1 2 0.5 0.5 1 1 35 c 30 c 25 c 20 c body thickness <2.1 mm including soics <18 pin all tqfps, tsops or all bgas <1 mm body thickness level 2a 17 28 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35 c 30 c 25 c 20 c level 3 8 11 14 20 5 7 10 13 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35 c 30 c 25 c 20 c level 4 7 9 12 17 4 5 7 9 3 4 5 7 2 3 4 6 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35 c 30 c 25 c 20 c level 5 7 13 18 26 3 5 6 8 2 3 4 6 2 2 3 5 1 2 3 4 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35 c 30 c 25 c 20 c level 5a 7 10 13 18 2 3 5 6 1 2 3 4 1 1 2 3 1 1 2 2 1 1 2 2 1 1 1 2 0.5 1 1 2 0.5 0.5 1 1 35 c 30 c 25 c 20 c

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